1. Technical Field
Embodiments of the invention relate to a semiconductor memory device. More particularly, embodiments of the invention relate to a semiconductor memory device having a self refresh mode and a related method of operation.
This application claims priority to Korean Patent Application 2005-7412, filed on Jan. 27, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
The semiconductor memory devices, such as Dynamic Random Access Memory (DRAM), used in mobile, battery powered host devices such as cellular telephone handsets or PDAs must operate with a minimum of power. Hence, low power memory devices are the norm, and as operating speeds for the various host devices increases the demand for power conservation in such low power memory devices increases. One aspect of low power memory device functionality being carefully considered in the quest for further reductions in power consumption is the refresh operation.
A refresh operation is required for volatile memory devices such as DRAM. Volatile memory devices are characterized by presence of an electrical charge on a capacitor associated with a memory cell in the memory device. Memory cell capacitors are not perfect in their form or function, and as a result, stored charge will escape as a leakage current. A refresh operation is periodically required to re-store charge to the memory cell capacitor. A conventional refresh operation may be viewed as a special “write” or re-write operation in which already stored data is read from memory and then written back into memory. The refresh operation takes place repeatedly a rate that precludes complete dissipation of the stored charge.
In order to maintain data stored in its memory cells, a memory device must periodically perform a refresh operation even when the host device or a memory system within the host device including the memory device is inactive. Thus, the refresh operation is always “on” making it a primary consideration in any attempt to reduce memory device related power consumption within the host device.
One conventional approach to minimizing the power consumption of a volatile memory device changes the period of refresh in accordance with sensed changes in the data retention period for memory cells in the memory device. This type of “self refresh” operation may monitor memory cell leakage current, and when a critical level of leakage current is sensed, a refresh operation is performed. Similarly, a critical stored charge value for the memory cells may be sensed and used to initiate a refresh operation. However, such “monitoring methods” generally operate under certain assumptions regarding average critical levels for leakage current or stored charge. They do not account for the presence of below-average or weak memory cells.
Additionally, some early conventional monitoring methods fail to account for the effects of changes in the ambient operating environment of the memory device. This is a significant oversight since memory cell leakage current varies with temperature. Thus, current conventional monitoring methods control the self refresh operation of a memory device in accordance with a temperature measured for the memory device by a temperature sensing circuit. The temperature sensing circuit may be on-chip or off-chip. Temperature controlled self refresh operations typically divide an expected operating temperature range into a plurality of temperature control zones and modify the period of the refresh operation in accordance with the current measured control zone, thereby prolonging the refresh cycle at low temperatures.
Obviously, the effectiveness of such temperature controlled, self refresh operations depends on the precision with which the actual operating temperature of the memory device is detected by the temperature sensing circuit.
One conventional temperature sensing circuit generally employs a band-gap reference circuit. See, for example, published U.S. patent application No. 2004-0071191 filed Apr. 15, 2004. Such a band-gap reference circuit enabled temperature sensing circuit comprises a diode terminal and a resistance terminal connected in parallel. Resistance magnitudes are matched in the circuit, such that currents flowing from these two terminals for a predetermined temperature will be equal. This result follows from an assumption that the respective terminal currents will be opposite one to another at the predetermined temperature.
In order to provide precise control over a self refresh operation using this type of temperature sensing circuit, fabrication process-induced variations in the circuit components must be accounted for. For example, a trimming operation is typically required to correct fabrication process-induced variations in a diode of the temperature sensing circuit. That is, before actual operation of the temperature sensing circuit, sensitivity reaction testing may be performed in relation to resistance and/or current change characteristics for the diode.
FIG. 1 illustrates a conventional temperature sensing circuit.
Referring to FIG. 1, a temperature sensing circuit 20 comprising a band gap reference circuit includes a temperature sensing unit 22 and a deviation temperature detecting unit 24. The temperature sensing unit 22 includes a current mirror type differential amplifiers DA1 and DA2, a subtraction resistance(Ra) terminal through which current is reduced in accordance with a temperature increase, an addition resistance terminal (R) through which current is increased in accordance with a temperature increase, and a comparator DA3 adapted to compare a test temperature with a sensed temperature and output a comparison result as a comparison output signal (Tout). The temperature sensing unit 22 also includes junction diodes D1 and D2 respectively coupled to differential amplifier DA1 and DA2. Junction diodes D1 and D2 may have different sizes and are thus represented in FIG. 1 as having a size ration of M to 1.
The deviation temperature detecting unit 24 includes a weighted resistance string comprising a plurality of binary weighted resistances RAi and RA4 through RA0 connected in series between the subtraction resistance (Ra) terminal and a ground terminal (VSS). Deviation temperature detecting unit 24 also includes a short switching circuit adapted to selectively short individual binary weighted resistances in response to test input signals or trimming address signals (Taddi and Tadd4 through Tadd0) applied to the deviation temperature detecting unit 24. In the illustrated example, the short switching circuit is constructed of N-type MOS transistors (Ni and N4 through N1) that are normally turned “OFF”.
Among the binary weighted resistances, resistance RA4 has a resistance value 16 times larger than the resistance value of resistance RA0. Resistance RA3 has a resistance value 8 times larger than the value of resistance RA0. Resistance RA2 has a resistance value 4 times larger than the value of resistance RA0. Resistance RA1 has a resistance value twice as large as the value of resistance RA0. The binary weighted resistances RAi and RA4–RA0 may be formed by patterning material such as polysilicon, for example.
In operation, for example, when resistance RA0 is shorted by turning transistor N0 “ON”, its resistance value is removed from the composite resistance value of the binary weighted resistances. Thus, current la flowing from the subtraction resistance terminal (Ra) to ground increases accordingly. In the conventional circuit, the removal of resistance RA0 is designed to adjust for an increase in temperature of 1□. The test input signals or trimming addresses may be designed accordingly to change a trip point for the temperature sensing circuit at a predetermined temperature while the circuit is operating in a test mode.
Similarly, as indicated by a logically high test input signal Tadd4, for example, the resistance RA4 may be shorted and thus removed from the composite resistance to thereby adjust the trip point to a temperature increases of 16□. Similarly, respective trimming address signals Tadd3, Tadd2, and Tadd1 may be used to selectively remove resistance RA3, resistance RA2, and resistance RA1 from the composite resistance in order to adjust the trip point for temperature increases of 8□, 4□, and 2□. In similar manner, the binary weighted resistances may be used to approximate a binary successive approximation method of control for temperature deviations having an error of less than 1□. An accurate trimming operation may thus be implemented.
In this conventional trimming operation applied to the conventional temperature sensing circuit, a Mode Register Set (MRS) signal is also provided in relation to the operation of the temperature sensing circuit. The MRS signal is applied as a drive signal to the temperature sensing circuit controlling the number of binary weighted resistances to be used in the temperature sensing circuit relative to the detection of a desired temperature. Once the MRS signal is established a fuse trimming operation may be performed to match the resulting composite resistance value and thereby correct for a fabrication process-induced variation in the diode.
However, the foregoing approach assumes that the trimming operation, as controlled in an MRS mode by an MRS signal, faithfully replicates actual operating conditions for the memory device. Where this assumption fails, the actual self refresh operation may not function as intended under actual operating conditions. That is, the temperature matched during the trimming operation may be different from the temperature of the actual self refresh operation, which may impede refresh and current characteristics for the memory device.
Accordingly, it would be beneficial to provide a memory device supporting an improved self refresh mode and related method of operation. The improved self refresh mode would be adapted to more precisely control its refresh period as a function of temperature, as between a trimming operation designed to correct fabrication process-induced variations and the actual operating temperature of memory device.